1. Field of Invention
The present invention relates to an electrostatic discharge (ESD) protection device of an integrated circuit. More particularly, the invention relates to a resistor that prevents noise interference from an input/output (I/O) pad for an analog signal.
2. Description of Related Art
ESD is often the main cause of integrated circuit (IC) damage in the process of fabricating the IC or after wafer fabrication is complete. For example, a human body walking on a carpet can carry a few hundred to a few thousand volts of electrostatic voltage at a higher relative humidity (RH), while tens of thousand electrostatic volts and above can be carried by the same human body at a relatively lower RH. When such a static electricity carrier comes in contact with a wafer, the discharged static electricity to the wafer probably causes wafer failure. Therefore, various methods to inhibit the electrostatic discharge (ESD) have been developed in order to prevent the ESD from damaging the wafer. The most common method is to inhibit the ESD by hardware, i.e. to design an ESD protection device between the internal circuit and each pad so as to protect the internal circuit.
FIG. 1 is a schematic diagram illustrating a conventional ESD protection circuit. Referring to FIG. 1, the ESD current input by the pad 100 is discharged through a MOS transistor 102 that leads a ground V.sub.SS so as to protect an internal circuit 104.
In an analog product, a heavily doped P+ resistor 106 is located between the I/O pad 100 and the internal circuit 104 to prevent noise interference.
FIG. 2 is a cross-sectional diagram showing the structure of the P+ doped resistor 106 in FIG. 1. Referring to FIG. 2, an N-well 110 is formed on a P-type substrate 108, while a P+ doped region 112 is formed in the N-well 110. The P+ doped region 112 is a resistor having a specific resistivity, wherein one end of which is connected to the pad 100 and the transistor 102, and the other end of which is connected to the internal circuit 104. With the N-well 10 serving as isolation, noise interference is prevented.
However, while testing the electrostatic protection device, a positive current is provided from the pad 100. As the P+ resistor 106 is similar to a PN diode with forward bias, it has an activating voltage far lower than the breakdown voltage (BV) of the transistor 102. As a result, the P+ resistor 106 can be activated by the positive current that passes through it. The ESD current is discharged through the P+ resistor 106 and flows into the substrate 108, causing the ESD protection device to fail. If the area of the P+ resistor 106 is too small, the P+ resistor 106 may easily be damaged. However, the die size may be increased if the area of the P+ resistor 106 is increased.